`timescale 1ns/1ns
module memory_tb;

	parameter WIDTH = 256;
	parameter PSIZE = 5;

	reg clk;
     	reg rst_n;
     	reg in_wr;
     	reg in_rd;
     	reg [WIDTH-1:0] in_data;
     	reg [PSIZE-1:0] in_wr_addr;
     	reg [PSIZE-1:0] in_rd_addr;
     	wire [WIDTH-1:0] out_data;

defparam memory.WIDTH = 256;
defparam memory.PSIZE = 5;

TOP	memory(
.clk(clk),
.rst_n(rst_n),
.in_wr(in_wr),
.in_rd(in_rd),
.in_data(in_data),
.in_wr_addr(in_wr_addr),
.in_rd_addr(in_rd_addr),
.out_data(out_data)
);

initial begin
	clk = 0;
	rst_n = 0;
	in_wr = 0;
	in_rd = 0;
	
	#100
	rst_n = 1;

	#100
	in_wr = 1;
	in_data = 100;
	in_wr_addr = 0;
	
	#100
	in_wr = 0;
	in_rd = 1;
	in_rd_addr = 0;

	#100
	in_rd = 0;
	in_wr = 1;
	in_data = 101;
	in_wr_addr = 0;

	#100
	in_data = 102;
	in_wr_addr = 1;
	
	#100
	in_wr = 0;
	in_rd = 1;
	in_rd_addr = 0;
	
	#100
	in_rd_addr = 1;

	#100
	$stop;
end

always #50 clk = ~clk;
endmodule 